Demand for embedded nonvolatile memory (NVM) in integrated circuits has grown steadily over the past decade. Desirable characteristics of embedded NVM include low cost, low power, high speed, and high reliability (data retention and program/erase cycling endurance). NVM may be embedded in various integrated circuit (IC) technologies such as, for example, the widely used Complementary Metal Oxide Semiconductor (CMOS) technology. Some embedded NVM in CMOS applications include, for example, storing: (1) chip serial numbers, (2) configuration information in ASICs (Application Specific Integrated Circuits), (3) product data, security information and/or serial numbers in radio frequency identification integrated circuits, (4) program code or data in embedded microcontrollers, (5) analog trim information, and the like.
Traditional embedded EEPROM (electrically erasable programmable read only memory) or Flash NVM memory technology use NMOS (n-channel Metal Oxide Semiconductor) memory cells (i.e. “nFET-based” nonvolatile memory cells). FIG. 1 is a cross-sectional diagram of a double-poly nFET-based nonvolatile memory (NVM) cell in accordance with the prior art. FIG. 1 shows an nFET-based nonvolatile memory cell 10 manufactured using a double-poly process (i.e. a fabrication process that forms a device having two layers of polysilicon). A first n+ doped region 12, formed in a p− doped substrate 14, embodies the source of the memory cell 10, and a second n+ doped region 16 embodies the drain of the memory cell 10. A channel region 18 extends between the source 12 and drain 16 regions. A polysilicon floating gate 20 is insulated from the channel region 18 and the substrate 14 by a gate dielectric layer 22. A polysilicon control gate 24 is insulated from the floating gate 20 by a second dielectric layer 26.
FIG. 2 is a cross-sectional diagram of a double-poly nFET-based NVM cell 10 in accordance with the prior art illustrating how channel hot-electron injection is used to inject electrons onto a floating gate of the device of FIG. 1. The memory state of the memory cell 10 is defined by the floating-gate voltage, VFG, which is varied by controlling the number of electrons stored on the floating gate 20. VFG is reduced by adding electrons to the floating gate 20. To add electrons to the floating gate 20, and thereby lower VFG, a large positive voltage (e.g., about 10V depending on the thickness of the dielectrics) is applied to the control gate 24 (i.e., the control gate is “pulled up”), while the drain 16 is positively biased (e.g., to about 5V depending on the thickness of the dielectrics) relative to the source 12.
Under these bias conditions, and as illustrated in FIG. 2, electrons are accelerated from the source 12, across the channel region 18, to the drain region 16. As the accelerated electrons traverse the channel 18 they collide with atoms of the semiconductor lattice and generate what are known as “hot electrons”. These hot electrons are attracted to the positive voltage applied to the control gate 24, and, by a process known as “channel hot-electron injection” (CHEI), are injected through the gate dielectric layer 22 and onto the floating gate 20. The floating-gate potential or voltage, VFG, is increased by removing electrons from the floating gate 20. To remove electrons from the floating gate 20, a large positive voltage (e.g., about 10V (depending on the thickness of the dielectric)) is applied to the source 12 of the memory cell 10 while the control gate 24 is either grounded or negatively biased. Under these bias conditions, a process known as Fowler-Nordheim (F-N) tunneling occurs, whereby electrons stored on the floating gate 20 are removed by F-N tunneling through the gate dielectric layer 22 and into the source 12.
Whereas nFET-based nonvolatile memory cells have been used for many years, it has been demonstrated that pFET-based nonvolatile memory cells exhibit a number of performance advantages over nFET-based nonvolatile memory cells. Some of these performance advantages include (1) increased program/erase cycle endurance (due to reduced oxide wear-out); (2) availability in logic CMOS processes (due to reduced memory leakage arising from more favorable oxide physics); (3) ability to easily store analog as well as digital values (due to availability of precise memory writes); and (4) smaller on-chip charge pumps (due to decreased charge pump current requirements.
FIG. 3 is a cross-sectional diagram of a conventional double-poly pFET-based NVM cell 28 in accordance with the prior art. A first p+ doped region 30, formed in an n− doped well 32 of a p− substrate 34, embodies the source of the memory cell 28, and a second p+ doped region 36 embodies the drain of the memory cell 28. A channel region 38 extends between the source 30 and drain 36 regions. A polysilicon floating gate 40 is insulated from the channel region 38 by a gate dielectric layer 42. A polysilicon control gate 44 is insulated from the floating gate 40 by a second dielectric layer 46.
Similar to the nFET-based nonvolatile memory cell 10 shown in FIG. 1, the memory state of the pFET-based nonvolatile memory cell 28 shown in FIG. 3 is defined by the floating-gate voltage, VFG, which is varied by controlling the number of electrons stored on the floating gate 40. To add electrons to the floating gate 40, and thereby lower VFG, the source 30 and n− doped well 32 are biased to about 3V, the drain 36 is biased to about −1.5V, and the control gate 44 is biased low enough that holes flow across the channel region 38.
FIG. 4 is a cross-sectional diagram of a double-poly pFET-based NVM cell in accordance with the prior art illustrating how impact-ionized hot-electron injection is used to inject electrons onto a floating gate of the device of FIG. 3.
Under these bias conditions, and as illustrated in FIG. 4, holes are accelerated from the source 30, across the channel region 38, and to the drain region 36. As the accelerated holes traverse the channel region 38 and enter a drain depletion region 48 in the vicinity of the drain 36/n− well 32 junction, the holes may collide with atoms of the semiconductor lattice and generate electron-hole pairs. This phenomenon is known as “impact ionization”. The generated holes are typically collected by the drain 36, while the generated electrons are expelled from the drain depletion region with a high kinetic energy attributable to a high electric field in the drain depletion region 48. Those high-energy electrons which collide with the semiconductor lattice may be scattered upward and, attracted by the higher potential of floating gate 40, and may then be injected into the conduction band of the gate dielectric layer 42 and onto the floating gate 40. This process is known as “impact-ionized hot-electron injection” (IHEI). Whereas the floating-gate voltage, VFG, is decreased by IHEI, the floating-gate voltage, VFG, is increased by removing electrons from the floating gate 40. To remove electrons from the floating gate 40, a voltage of approximately 10V (depending upon the thickness of the dielectric) is applied to one or more of the source 30, n− well 32 (via n− well contact 33 which may be an n+ region), and drain 36, while the control gate 44 is typically grounded. Under these bias conditions, Fowler-Nordheim tunneling occurs and electrons stored on the floating gate 40 tunnel through the gate dielectric layer 42 and into the source 30, n− well 32 and/or drain 36 regions.
Although pFET-based nonvolatile memory cells have significant performance advantages over nFET-based nonvolatile memory cells, pFET-based nonvolatile memory cells can be troubled by a phenomenon often referred to as the “stuck bit” phenomenon. Stuck bits in pFET-based nonvolatile memory cells manifest themselves as follows.
Certain pFET-based nonvolatile memory cells use Fowler-Nordheim tunneling to raise the floating-gate voltage, VFG, and IHEI to lower VFG. One requirement of IHEI, however, is that the pFET channel must be conducting current so that electrons can be generated by impact ionization and injected onto the floating gate. If the channel is not conducting then IHEI cannot ensue and, consequently, electrons cannot be injected onto the floating gate of the pFET-based nonvolatile memory cell in order to program it. There are two primary ways in which a channel can be rendered insufficiently conducting to support IHEI. First, post-fabrication charge stored on the floating gate of a memory cell may prevent a conducting channel from forming. Second, a once established conducting channel may be removed by way of excessive erasure of the memory cell by Fowler-Nordheim tunneling. Effectively, by “overtunneling” the memory cell, the memory cell becomes “stuck” in an off state, and, in the absence of channel current, no electron injection can be performed to lower the floating-gate voltage. In any circumstance, if the floating-gate voltage, VFG, is raised so high that the pFET is turned off, there will be insufficient channel current to program the memory cell, and the memory value of the memory cell is said to be “stuck”.
To avoid the stuck bit problem, conventional double-poly pFET-based nonvolatile memory cells take advantage of the presence of a control gate (e.g. as discussed above in connection with FIG. 3) to help ensure that a conducting channel is maintained to support IHEI. By applying an appropriate voltage to the control gate while tunneling electrons off of the floating gate, a sufficiently conducting channel can be maintained for subsequent writes to the memory cell.
Whereas double-poly pFET-based nonvolatile memory cells are able to use the control gate to avoid the stuck bit problem, their use is limited by not being easily integrated in standard logic CMOS processes, which are typically single-poly processes.
FIG. 5 is a cross-sectional diagram of a single-poly-based NVM cell in accordance with the prior art which attempts to overcome limitations associated with the double-poly pFET-based NVM cell shown in FIG. 3 by using a specially formed control-gate structure. In FIG. 5 a single-poly pFET-based nonvolatile memory cell 50, as disclosed in U.S. Pat. No. 5,761,121, attempts to overcome the limitations of the double-poly pFET-based nonvolatile memory cells. The pFET-based nonvolatile memory cell 50 includes a storage transistor 52, having a drain 54, a source 56, and a floating gate 58. The pFET-based nonvolatile memory cell 50 also includes a separate control-gate structure 60, having a control-gate implant 62. Drain region 54 is surrounded by drain depletion region 64 and, like source region 56 and control gate implant 62 (which may be p doped) is disposed in n− well 66 of p− substrate 68. Unfortunately, although pFET-based nonvolatile memory cell 50 does not require a double-poly CMOS process, it does require additional processing steps to form the control-gate structure 60, thereby negating many of the benefits of standard-CMOS compatibility and causing higher manufacturing costs and potentially lower yields.
What is needed, therefore, are programming methods and structures that avoid stuck bits in pFET-based nonvolatile memory cells, the structures of which are compatible with standard single-poly CMOS fabrication processes and do not require custom masking and fabrication steps beyond that employed in standard CMOS fabrication processes.